Several programs have been underway to increase the density of integrated circuits. One of these programs, the very high speed integrated circuit (VHSIC) program, is directed toward delivering electronics utilizing very large scale integrated circuit (VLSI) techniques to provide more advanced and smarter systems. Some of the older VLSI programs have a performance specification of five.times.10.sup.13 gate-Hz/cm.sup.2 functional throughput rates. In order to achieve this type of performance, lithographic equipment that draws ultrafine lines must be built, and the requisite packages created. These chips will have features as small as 0.5 micrometers which can result in a chip having between 20,000 to 40,000 gates and 100,000 to 400,000 transistors on chips ranging as large as 0.25 square inches. They will be mounted on carriers having between 150 to 400 pins.
One of the largest challenges to developing high density VLSI devices is testing. Because of the complex circuit functions and/or large quantities of circuit functions that may be present in a VLSI circuit, or in a system that employs VLSI circuits, testing methods have themselves become very sophisticated and complex. In addition, complex test methods generally require corresponding complex equipment, including software, and become increasingly expensive and burdensome to carry out. However, in order to ensure a relatively high degree of reliability for a given chip design, it is necessary to design for testing to ensure that a high percentage of the faults are detectable. Present goals for fault detections are 98% or greater.
One of the best known test methods for testing large scale integrated circuits is level sensitive scan design (LSSD) which is well described in the literature. See U.S. Pat. No. 4,519,078, issued to Donald Komonytsky and assigned to Storage Technology Corporation for a general description of LSSD. See also U.S. Pat. No. 4,428,060, issued to A. Blum and assigned to International Business Machines, and E. J. McCluskey, "A Survey of Design for Testability Scan Techniques", VLSI Design, Dec. 1984, pp. 38-61, for a comprehensive list of patents and publications for the testing of electronic structures. Basically, LSSD utilizes a plurality of controllability/observability points internal to an LSI circuit. Controllability is provided by allowing data to be shifted into these points which are comprised of shift register latches (SRL's) in a serial manner. A test is then performed and then the data stored in the SRL's and shifted back out for observation thereof. Therefore, control/observation of an LSI circuit no longer depends on the number of pins in the package. Furthermore, because the latches themselves are part of the internal circuit, they can be utilized to break feedback paths in a sequential circuit, enabling the test for the combinational circuits between SRL's to be generated automatically.
In a typical scan design, the shift registers are located at specific points required for the design function but are connected together in a scan chain for testing purposes. The scan chain allows for realization of any test state in the registers for test application. A test pattern is then generated on a computer. The generated test pattern is then shifted into the SRL's, test vectors (selected words or groups of digital data) applied to the primary inputs or pins of the chip, the system clocks applied to perform the test, the primary output pins compared to expected vector outputs and data scanned out of the SRL's to compare it to known good test vectors. In performing this test, numerous series of test vectors are usually required for shifting into the SRL's, applying the test vectors and then shifting the results back out. This becomes somewhat time consuming when applying these tests on a conventional tester.
In conventional scan designs, the SRL's are connected in a continuous string, as illustrated in U.S. Pat. No. 4,519,078, or implemented in a parallel manner, as illustrated in U.S. Pat. No. 4,503,537, issued to William McAnney and assigned to International Business Machines Corporation. In the sequential design, a predetermined amount of time is required to test a given chip. The amount of time required to shift data into the SRL's to perform the test and shift the data out is determined by the number of SRL's in the serial chain. If only one function of the chip were to be tested, data would have to be shifted through all of the shift registers in the chain in order to test this function. For example, if a chip had multiple functions and one function required loading and unloading of the shift registers four times as compared to another function which required loading and unloading of the SRL's six times to perform the appropriate test, the shift registers for the first function would have to be loaded and unloaded an additional two times to perform the final two passes for the test pattern of the second function. The time required to shift through the registers in the first function for these additional two passes is wasted time. In addition to the additional time, additional logic is required to connect the registers together. This is true even if the registers can be more easily loaded and unloaded using the normal logic flow. This extra logic can become a primary disadvantage, especially if the registers are connected to buses.
In view of the above disadvantages, there exists a need for a test method which utilizes scan techniques that reduce the time required to scan data into the control/observation points and also reduce the time for generation of the test patterns.